FIG. 10 shows a conventional semiconductor device structure which is exemplified by a CMOS inverter circuit which acts as one of electronic circuits for use in a semiconductor device. FIG. 10(a) diagrammatically shows a section of the CMOS inverter circuit and FIG. 10(b) shows a plan view thereof. For simplification, illustration of lines 8 to 11 is omitted from FIG. 10(b).
In FIG. 10(a), 1 denotes a p-type semiconductor substrate where an electronic circuit is formed; 2 denotes an n-type impurity region formed in the p-type semiconductor substrate 1; 3a and 3b denote high-concentration p-type impurity regions formed in the n-type impurity region 2; 4a and 4b denote high-concentration n-type impurity regions formed in the p-type semiconductor substrate 1; 5 denotes gate insulating films of SiO2 or the like for insulation between a gate electrode 6 and the p-type semiconductor substrate 1 and between a gate electrode 7 and the n-type impurity region 2, respectively; and 6 and 7 denote the gate electrodes formed on the gate insulating films 5, respectively.
Herein, the n-type impurity region 2, the high-concentration p-type impurity regions 3a and 3b, and the gate electrode 7 form a p-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor). On the other hand, the semiconductor substrate 1, the high-concentration n-type impurity regions 4a and 4b, and the gate electrode 6 form an n-channel MOSFET. A gate line 8 is connected to the gate electrodes 6 and 7 of the n-channel MOSFET and the p-channel MOSFET and serves to apply a common voltage as an input signal of the CMOS inverter circuit while an output line 9 is connected to the drain electrode (high-concentration p-type impurity region 3a) of the p-channel MOSFET and the drain electrode (high-concentration n-type impurity region 4b) of the n-channel MOSFET to produce an output signal of the CMOS inverter. Power supply lines 10 and 10 are connected to the source electrode (high-concentration n-type impurity region 4a) of the n-channel MOSFET and the source electrode (high-concentration p-type impurity region 3b) of the p-channel MOSFET, respectively, to provide electric voltages.
The operation of this CMOS inverter circuit will be described. In the illustrated CMOS inverter circuit comprising the p-channel MOSFET and the n-channel MOSFET of FIG. 10(a), the power supply line 10 which is connected to the source electrode of the n-channel transistor is grounded (0V) and the power supply voltage (e.g. 5V) is applied to the power supply line 11 connected to the source electrode of the p-channel transistor.
When an input signal of 0V is applied to the gate line 8, the n-channel transistor is turned off while the p-channel transistor is turned on. Therefore, the power supply voltage (5V) is given to the power supply line 11 and is output to the output line 9. On the other hand, when the input signal of 5V is applied to the gate line 8, conversely to the above case, the n-channel transistor is turned on while the p-channel transistor is turned off. As a result, the ground voltage (0V) which is given to the power supply line 10 is output to the output line.
In this CMOS type circuit, the current hardly flows in the transistors when the output does not change and it mainly flows when the output changes. That is, when the gate line 8 becomes 0V, an output current for charging the output line 9 flows through the p-channel transistor, while, when the gate line 8 becomes 5V, an output current for discharging the charge of the output line 9 flows through the n-channel transistor. In this manner, the CMOS circuit of FIG. 10(a) is formed as an inverter circuit adapted to output a signal with a polarity reverse to that of the input. In this inverter circuit, it is necessary to cause the same current to flow in the p-channel transistor and the n-channel transistor for equalizing the rising speed and the falling speed upon switching.
However, for example, on the (100) plane, the mobility of holes serving as carriers in the p-channel transistor is lower than that of electrons serving as carriers in the n-channel transistor and the ratio is 1:3. Therefore, if the p-channel transistor and the n-channel transistor have the same area, there occurs a difference in current driving capability therebetween and thus the operating speeds cannot be the same. Accordingly, as shown in FIG. 10(b), the areas of the drain electrode 3a, the source electrode 3b, and the gate electrode 7 of the p-channel transistor are set larger than those of the drain electrode 4b, the source electrode 4a, and the gate electrode 6 of the n-channel transistor corresponding to their mobility ratio to substantially equalize the current driving capabilities, thereby making the switching speeds equal to each other. However, this needs to widen the area occupied by the p-channel transistor by three times that of the n-channel transistor and thus the areas occupied by the p-channel transistor and the n-channel transistor become unbalanced, which has been a barrier to improve integration degree of semiconductor devices.
As a prior document relating to improvement in current driving capability of a p-channel transistor, there is Patent Document 1 mentioned below. In Patent Document 1, the current driving capability of a p-channel transistor is improved by using the (110) plane. Further, Patent Document 2 describes that the current driving capability of a p-channel transistor is improved by using an SOI substrate and forming an accumulation-mode p-channel transistor on the SOI substrate. However, when an arbitrary substrate is used, it is impossible to actually equalize the current driving capabilities of an n-channel transistor and a p-channel transistor having the same size in an ON-state. Further, in the accumulation-mode transistor disclosed in Patent Document 2, a substrate electrode is essential in addition to a gate electrode and a voltage adapted to form a depletion layer in a channel region to pinch off a channel should be applied to both electrodes, and therefore, there has been a drawback in that it is complicated in terms of structure and circuit.    Patent Document 1: Japanese Unexamined Patent Application Publication (JP-A) No. 2003-115587    Patent Document 2: Japanese Unexamined Patent Application Publication (JP-A) No. Hei 07-086422